Board Control and Status Register - BCSR
Table 5-15. External Tool Revision Encoding
TOOLREV(0:3) [hex]
0
1
2
3-F
External Tool Revision
ENGINEERING
PILOT
A
Reserved
5.11.4 BCSR3 Board Control - Status Register 3
BCSR3 is a control register which is accessed at offset 0xC from the BCSR base address.
Its a read- write register which may be read or written at any time 1 . BCSR3s’ various fields
are described in Table 5-16
Table 5-16. BCSR3 Description
BIT
0
MNEMONIC
USB_EN
Function
USB Port Enable . When asserted ( low ) the USB chip connected to SCC4
PON
DEF
1
ATT.
R/W
is enabled for transmission and reception. When negated, the USB
transceiver is in standby mode and its associated buffers 1 are in tri-state
mode, freeing all its i/f signals for off-board use via the expansion
connectors.
1
USB_HI_SPEED
USB Hi Speed . When asserted ( low ) the USB chip connected to SCC4 is
0
R/W
set for hi speed (12 Mbps) transmission and reception. When negated, the
USB transceiver is set to low speed (1.5 Mbps) transmission and reception
2
USBVCC0
USB Port VCC EN . When asserted ( high ), 5V power is applied to the USB
0
R/W
Bus. When negated, power to the USB port is disconnected.
3
FETHIEN2
Fast Ethernet Port 2 Initial Enable . When asserted ( low ) the DM9161’s
1
R/W
MII port, residing on FCC3, is enabled after Power-Up or after FETH_RST
is negated. When negated ( high ), the DM9161’s MII port is isolated after
Power-Up or after FETH_RST is negated and all i/f signals are tri-stated.
After initial value has been set, this signal has no influence over the
DM9161 and MII isolation may be controlled via MDIO 0.10 bit.
4
FETH2_RST
Fast Ethernet port 2 Reset . When active ( low ) the DM9161 is reset. This
1
R/W
line is also driven by HRESET signal of the PowerQUICC II. Since MDDIS
pin of the DM9161 is driven low with this application, the negation of this
signal causes all the H/W configuration bits to be sampled for initial values
and device control is moved to the MDIO channel, which is the control path
of the MII port.
5
ATM16
ATM 16 bit UTOPIA . When asserted ( low ) the UTOPIA is set for 16 bit.
1
R/W
When negated ( high ), the UTOPIA is set for 8 bit.
6
ATM_SINGLE_PH
ATM SINGLE PHY . When asserted ( low ) the UTOPIA is set to Multi PHY.
1
R/W
Y
When negated ( high ), the UTOPIA is set for Single PHY.
1 Provided
that BCSR is not disabled.
Chapter 5. Module Design
相关PDF资料
MPC8308-RDB BOARD REF DESIGN MPC8308
MPC8309-KIT KIT EVALUATION FOR MPC830X
MPC8315E-RDB PROCESSOR BOARD PWRQUICCII PBGA
MPC8349E-MITX-GP KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE BOARD REFERENCE FOR MPC8349
MPC8377E-MDS-PB BOARD MODULAR DEV SYSTEM
MPC8569E-MDS-PB BOARD MOD DEV SYSTEM MPC8569
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